General purpose input/output (GPIO) enables an integrated circuit designer to provide generic pins that may be customized for particular applications. For example, a GPIO pin is programmable to be either an output or an input pin depending upon a user's needs. A GPIO module or peripheral will typically control groups of pins which can vary based on the interface requirement. Because of the programmability of GPIO pins, they are commonly included in microprocessor and microcontroller applications. For example, an applications processor in mobile devices may use a number of GPIO pins to conduct handshake signaling such as inter-processor communication (IPC) with a modem processor.
With regard to such handshake signaling, a sideband signal is deemed as “symmetric” if it must be both transmitted and received by a processor. If there are n symmetric sideband signals that need to be exchanged, each processor requires n*2 GPIOs (one GPIO to transmit a given signal and one GPIO to receive that signal). For example, a symmetric IPC interface between a modem processor and an application processor may comprise five signals, which translates to 10 GPIO pins being necessary for the resulting IPC signaling. The need for so many GPIO pins for IPC communication increases manufacturing cost. Moreover, devoting too many GPIOs for IPC limits the GPIO availability for other system-level peripheral interfaces. The problem cannot be solved by moving the IPC communication onto the main data bus between the processors in that certain corner conditions are then violated.
To alleviate the pin demands suffered by conventional GPIO systems, a “virtual” GPIO architecture has been developed such in which multiple GPIO signals are serialized onto a single transmit pin such as through a finite state machine (FSM). The FSM receives the multiple GPIO signals from a GPIO interface that in turn receives the multiple GPIO signals from a processor. The GPIO interface also interfaces with conventional GPIO pins that transmit conventional GPIO signals. The distinction between the conventional GPIO signals and the virtual GPIO signals carried on the transmit pin is transparent to the processor. This is quite advantageous in that the processor needs no software modification to communicate through the GPIO interface. With regard to transmission, the processor thus presents a set of GPIO signals to the GPIO interface. Depending upon the number of conventional GPIO pins available, the GPIO interface will transmit a first subset of the GPIO signals over corresponding conventional GPIO pins. In contrast, the GPIO interface presents a remaining subset of the GPIO signals to the FSM, which serializes them and transmits them over the dedicated transmit pin.
During GPIO signal transmission, the dedicated transmit pin couples through a suitable transmission line such as a circuit board trace to a receiving integrated circuit's dedicated receive pin. A transmitting integrated circuit thus also includes a dedicated receive pin for receiving transmitted virtual GPIO signals from a remote integrated circuit. The FSM deserializes the received virtual GPIO signals into a first set of received GPIO signals that are presented to the GPIO interface. Similarly, the GPIO interface receives a second set of received GPIO signals through the conventional GPIO pins. The first and second set of received GPIO signals may then be presented to the processor in a conventional fashion through the GPIO interface. To the processor, it is thus transparent whether a given received GPIO signal was received on the dedicated receive pin as a virtual GPIO signal or over a conventional GPIO pin. The processor thus needs no software modification with regard to transmission or reception.
With regard to this advantageous virtual GPIO capability, note that a receiving circuit may not be ready to receive a frame of virtual GPIO signals (nor to receive conventional GPIO signals). Flow control allows such a receiving integrated circuit to indicate to the transmitting integrated circuit whether or not the receiving integrated circuit is able to currently receive data. In general, however, flow control requires the use of additional pins. For example, a universal asynchronous receiver transmitter (UART) interface includes a request to send (RTS) pin as well as a clear to send (CTS) pin. These two flow control pins are in addition to a dedicated receive pin as well as a dedicated transmit pin. The two additional flow control pins (RTS and CTS) for a UART interface thus increases pin count and contributes to higher manufacturing cost.
Accordingly, there is a need in the art for a GPIO architecture that can transmit and receive a plurality of GPIO signals using just a two-pin interface in which the flow control is multiplexed over the two-pin interface. More generally, there is a need in the art for multiplexed flow control for two-pin interfaces.